1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor integrated circuit having a mode selection circuit compatible for diverse package types.
2. Description of the Related Art
Recently, a semiconductor integrated circuit such as Dynamic Random Access Memory (DRAM) includes a plurality of semiconductor chips (or dies) that are stacked and packaged to obtain a larger capacity in the same area. Meanwhile, a semiconductor integrated circuit having a single semiconductor chip packaged is referred to as a single die package (SDP), a semiconductor integrated circuit having two semiconductor chips stacked and packaged is referred to as a dual die package (DDP), and a semiconductor integrated circuit having four semiconductor chips stacked and packaged is referred to as a quad die package (QDP).
FIG. 1 is a configuration diagram illustrating an interface structure of a conventional SDP. FIG. 2 is a configuration diagram illustrating an interface structure of a conventional DDP.
Referring to FIG. 1, a semiconductor chip 10 included in the SDP includes an internal circuit 12 configured to perform given operations according to a first chip select signal CS0#, a first clock enable signal CKE0, a first on-die termination (ODT) control signal ODT0, and a first ZQ calibration control signal ZQ0. Address signals ADD<15:0>, command signals RAS#, CAS#, and WE#, and data DQ<7:0> are also inputted to the internal circuit 12 for the given operations.
Here, the first chip select signal CS0#, the first clock enable signal CKE0, the first ODT control signal ODT0, and the first ZQ calibration control signal ZQ0 are inputted through corresponding pads. Furthermore, another pads for inputting a second chip select signal CS1#, a second clock enable signal CKE1, a second ODT control signal ODT1, and a second ZQ calibration control signal ZQ1 are reserved.
Referring to FIG. 2, the DDP includes a first semiconductor chip 20 and a second semiconductor chip 30, which are stacked vertically. The first semiconductor chip 20 includes a first internal circuit 22 configured to perform given operations based on a first chip select signal CS0#, a first clock enable signal CKE0, a first ODT control signal ODT0, and a first ZQ calibration control signal ZQ0. The second semiconductor chip 30 includes a second internal circuit 32 configured to perform given operations based on a second chip select signal CS1#, a second clock enable signal CKE1, a second ODT control signal ODT1, and a second ZQ calibration control signal ZQ1.
Here, the first chip select signal CS0#, the first clock enable signal CKE0, the first ODT control signal ODT0, and the first ZQ calibration control signal ZQ0 are directly inputted to the first semiconductor chip 20. On the other hand, the second chip select signal CS1#, the second clock enable signal CKE1, the second ODT control signal ODT1, and the second ZQ calibration control signal ZQ1 are transmitted to the second semiconductor chip 30 through the first semiconductor chip 20. Furthermore, the second chip select signal CS1#, the second clock enable signal CKE1, the second ODT control signal ODT1, and the second ZQ calibration control signal ZQ1 are transmitted through signal lines twisted in the first semiconductor chip 20, when the signals are transmitted from the first semiconductor chip 20 to the second semiconductor chip 30. The respective signals CS1#, CKE1, ODT1, and ZQ1 are inputted to corresponding pads provided in the second semiconductor chip 30.
FIG. 3 is a configuration diagram illustrating an interface structure of another conventional DDP (3DS DDP).
Referring to FIG. 3, the 3DS DDP includes a first semiconductor chip 40 and a second semiconductor chip 50, which are stacked vertically. The first semiconductor chip 40 includes a first internal circuit 42 configured to perform given operations based on a first chip select signal CS0#, a first clock enable signal CKE0, a first ODT control signal ODT0, and a first ZQ calibration control signal ZQ0. The second semiconductor chip 50 includes a second internal circuit 52 configured to perform given operations based on a second chip select signal CS1#, the first clock enable signal CKE0, the first ODT control signal ODT0, and a second ZQ calibration control signal ZQ1.
Here, the first chip select signal CS0#, the first clock enable signal CKE0, the first ODT control signal ODT0, and the first. ZQ calibration control signal ZQ0 are directly inputted to the first semiconductor chip 40. On the other hand, the second chip select signal CS1#, the first clock enable signal CKE0, the first. ODT control signal ODT0, and the second ZQ calibration control signal ZQ1 are transmitted to the second semiconductor chip 50 through the first semiconductor chip 40. Furthermore, the second chip select signal CS1# and the second ZQ calibration control signal ZQ1 are transmitted through signal lines twisted in the first semiconductor chip 40, when the signals are transmitted from the first semiconductor chip 40 to the second semiconductor chip 50. This is to input the second chip select signal CS1# and the second ZQ calibration control signal ZQ1 to corresponding pads provided in the second semiconductor chip 30. Meanwhile, the first clock enable signal CKE0 and the first ODT control signal ODT0 are transmitted through straight signal lines, when the signals are transmitted from the first semiconductor chip 40 to the second semiconductor chip 50. The first and second semiconductor chips 40 and 50 commonly use the first clock enable signal CKE0 and the first ODT control signal ODT0. Furthermore, the pads of the first and second semiconductor chip 40 and 50 corresponding to a second clock enable signal CKE1, a second ODT control signal ODT1 are reserved.
In the conventional DDP illustrated in FIG. 2, the chip select to signal, the clock enable signal, the ODT control signal, and the ZQ calibration control signal are inputted to each of the semiconductor chips. In the conventional 3DS DDP illustrated in FIG. 3, however, the chip select signal and the ZQ calibration control signal are inputted to each of the semiconductor chips, and the clock enable signal and the ODT control signal are inputted to the semiconductor chip group.
Meanwhile, the QDP (not illustrated in the FIGS. 1 to 3) may also have interface structures corresponding to various cases as in the DDPs illustrated in FIGS. 2 and 3.
However, since the semiconductor chips included in the SDP, the DDP, and the QDP having the above-described configurations have various interface connection structures, the semiconductor chips must be fabricated through different mask processes depending on package types SDP, DDP, and QDP and package designs. Thus, the productivity of the semiconductor chip fabrication process inevitably decreases.